Conventionally, when the memory cells of a memory plane of a memory are connected in a differential mode between two bit lines one of the bit lines, during a read operation and after having been precharged to a high voltage, is discharged (drawn to ground) while the other bit line is assumed to remain at its high precharge state. However, in reality, this other bit line is also drawn to ground on account of leakage currents from the other memory cells connected to this other bit line. Additionally, the leakages are all the more significant as the number of memory points on the same column stores the information based upon inverse to the value read. This causes a reduction in the voltage difference between the two bit lines.
Customarily, the memory is equipped with a reference path (dummy path) for temporally auto-adjusting the delivery of a signal for activating the read amplifiers respectively disposed at the foot of the columns of the memory plane. These read amplifiers amplify the voltage difference present between the two bit lines during the read operation.
This reference path customarily comprises a reference column formed of two bit lines to which are connected reference memory cells. At least one of the reference memory cells is activated by a reference word line (dummy word). One of the reference bit lines, namely the one which is intended to be discharged upon the activation of the reference cell, is used to generate a signal for activating the read amplifiers.
Moreover, to compensate for the effects of the leakage currents mentioned above, and to obtain a memory operating within a high temperature span in particular, a delay circuit for delaying the delivery of the signal for activating the read amplifiers is generally inserted into the reference path to obtain a correct operation of the memory in a worst-case situation. A worst-case situation may be, for example, a very high temperature for which the leakage currents are significant. However, such an approach, if it leads to an acceptable performance in the worst-case situation, limits the performance of the memory in intermediate and normal operating situations.